Dream team has developed an architecture of a new smart vision system called BiSeeMos. This smart camera is designed for stereo vision purposes and the implementation of a simple dense stereo vision algorithm. In addition, the architecture has been designed for dedicated parallel algorithms by using a high performance FPGA. This chip provides the user with useful features for vision processing as integrated RAM blocks, embedded multipliers, phase locked loops and plenty of logic elements.

For further information on BiSeeMos architecture including hardware features and design strategies, please read the following article: BiSeeMos. In this article, "Stereo Vision Algorithm Example" is examined in order to demonstrate the efficiency of this platform in real time processing.

More recently two others stereo Smart camera have been done:

• BiSeeMOS II is lighter the the previous one. The FPGA is EP3C16 with only 1 SRAM Block of 1MWord. Communication link is performed by an embedded USB2.0 chip.

  

• BiSeeMOS III is a compromise between the two first ones. It includes a CycloneIII EP3C40 and its size is that of coarsly BiSeeMOS II.

  

SeeMos platform is dedicated to active vision and in particular to the early vision process. Thus, the SeeMos platform which constitutes an embedded system is composed of a modular hardware and a software design.

The main feature of this platform is an architecture based on FPGA, CMOS imager, Inertial devices, High speed communication and a DSP-based Codesigned board.

The main purpose of our architecture is to allow the implementation of early vision processes as in the human or primate visual system. In these systems it is well known that the first neural layers (in the retina) pre-filter the visual data flow in order to select only the conspicious information.

This Prefiltering step needs strong parallelization, on one hand to respect real-time constraints, and on the other hand because of the intrinsic characteristics of the algorithms. For exemple, some classical algorithms in an attention task used to elaborate an efficient saliency map are motion detection, Gabor filters, and color segmentation. However, the characteristics of particular visual tasks may require dedicated image processing and only an FPGA approach allows such flexibility. For architectures such as these, a Stratix EP1S60 from Altera has been chosen. The need for strong parallelization was what led us to connect 5x2MB SRAM synchronous memory blocks. In our approach, the high-level processing has to be performed on a host computer rather than on the embedded system.

OmniMOS is an old smart camera dedicated to omni-directional vision. It builds with a fovea-based image sensor associated to paraboloidal reflector.

The image sensor named "Amovite" and built by Fillfactory provided a foveal image. In such sensor, the photosites are arranged in concentric rings and with a size varying linearly with the distance from the geometric center.

The router is associated to a DMA (Direct Memory Access) module. DMA enables both hardware packet injection from local node memory into the network, and symmetrically, hardware packet rejection from the network into local node memory. Packet headers are automatically added and removed by the DMA hardware module. The router uses a wormhole routing technique using buffers that enable to handle a small part of a packet. We have chosen this routing technique in order to minimize communication latency.

More information will be posted regarding the IP (VHDL code, Datasheet, TestBench,..).

Download Ver 1.1